Synchronous sequential systems, such as synchronous dynamic random access memories (SDRAMs) and specific Double Data Rate (DDR) memories, rely on globally synchronized clocks. As CPU speeds increase, low-skew clock distributions are becoming increasingly important to increase the speed at which data can be transmitted to and from semiconductor devices. Many devices commonly employ on-chip delay-lock loops (DLL) and phase-lock loops (PLL) to improve input/output timing margins by achieving low skew distributions.
FIG. 1 illustrates an example of a prior art common synchronized clock distribution circuit. A clock 102 provides a source clock signal and is input into a synchronization circuit 104. In order to synchronize the clock 102, a destination clock signal (feedback signal) 106 simulating a delay in the destination clock is returned to the synchronization circuit 104 and a clock signal delay through the synchronization circuit 104 is adjusted or modified until the destination clock signal 106 and the source clock signal are substantially synchronized. Furthermore, the destination clock signal 106 may be distributed to additional devices such as devices 108, 110, 112, 114.
Synchronization circuit 104 generally adequately synchronizes only a single device 112 and may additionally adequately synchronize an immediately adjacent device such as device 114. However, because the clock 102 is only synchronized for devices 112, 114, devices 108, 110 must be designed to exhibit a substantially equivalent load such as by positioning devices 108, 110 at almost exactly the same distance from the synchronization circuit 104 and forming the delay paths and the devices from substantially similar materials and components to cause the delay to be substantially equivalent. As semiconductor chips get bigger and operate at higher frequencies, the differences in distance, materials and components between devices 108, 110 and 112, 114 may cause devices 108, 110 to be inadequately synchronized with devices 112, 114.
In order to address the problems that arise from differences in destinations, some devices have incorporated the use of an independent synchronization circuit for each different device or destination. FIG. 2 illustrates an example of a prior art synchronized clock distribution circuit employing two independent synchronization circuits with one for each destination. The first destination, including devices 108 and 110, is synchronized to the source clock signal through the first synchronization circuit 202. The second destination, including devices 112 and 114, is synchronized to the source clock signal through the second synchronization circuit 204. This solution is generally effective in providing synchronized clock distribution to all the devices. However, with electronic devices becoming more complex, circuitry area or space, also termed “real estate,” in semiconductor devices is becoming more and more scarce. The solution described in FIG. 2 requires twice as much circuit area as the example in FIG. 1 since synchronization circuits are required for each of the two destinations. Furthermore, additional synchronization circuits increase costs and power consumption for the device or system in which the two circuits are utilized.
In view of the shortcomings in the prior art, it would be useful to provide a method and apparatus capable of synchronizing each destination according to the unique configuration within the semiconductor device.